PCI Express lanes, LTSSM training and the PIPE interface
How PCI Express lanes are counted, what happens during LTSSM link training, and what the PIPE interface exposes between the link layer and the physical layer.
- Published: 12 September 2026
- Editorial guide
- By Editorial Desk
A PCI Express link is built from one or more lanes, and each lane is a pair of differential signals, one direction for transmit and one for receive. The link width is the number of lanes that both ends agree to use after training, so a device that supports four lanes can come up as x4, x2, or x1 depending on what the other side offers and what the link can negotiate. The width is not fixed by the connector alone: it is the result of a negotiation that happens every time the link trains.
How do PCI Express lanes work?
A lane carries a serial bit stream, and the two directions are independent. Each direction has its own transmitter and receiver, its own clock recovery, and its own equalization settings. That is why a link can be asymmetric in principle, though most implementations keep the same width in both directions.
The number of lanes is usually written as x1, x2, x4, x8, or x16. A slot may be physically long enough for sixteen lanes but wired for fewer, and a card may have a connector that fits a larger slot while using only part of it. The specification separates the mechanical form from the electrical width, so you should read the slot description and the device description separately.
Lanes are counted per link, not per device. A root complex can expose several root ports, each with its own link, and a switch can fan out one upstream link into several downstream links. When you read a block diagram, the number next to each connection is the trained width of that particular link, not a property of the chip as a whole.
For a closer reading of how lanes are grouped and counted, PCI Express lanes are described from the published specifications alongside the topology that surrounds them. The same source treats the root complex, root ports, switches, and endpoints as separate pieces, which helps when you are trying to work out which link a given number belongs to.
What happens during LTSSM link training?
LTSSM stands for Link Training and Status State Machine. It is the sequence of states that a link passes through from power-on or reset until it is ready to carry normal traffic. The states are defined in the specification, and each one has an entry condition and a set of allowed transitions.
The first states deal with detection. The transmitter and receiver check whether a partner is present on the other end of the lane, and whether the electrical conditions look sane. If nothing is detected, the link stays in a low-power or idle condition and does not attempt to move forward.
Once a partner is detected, the link moves into polling and configuration. During polling, the two sides exchange ordered sets so they can agree on bit lock and symbol lock. During configuration, they exchange information about the number of lanes each side can support, the link number, and the lane numbering. This is where the final width is decided: both sides propose a width, and the link settles on a value that both can use.
After configuration comes the transition to the L0 state, which is the normal operating state. Before that, the link may pass through recovery states if the signal quality is not good enough. Recovery is where equalization is adjusted and where the link can renegotiate if errors appear later. A link that drops out of L0 during operation will usually go back through recovery rather than starting from detection again.
The frame-by-frame view matters because training is not a single event. It is a sequence of ordered set exchanges, each with its own timing and its own response. If you are reading a trace or a compliance log, the state names tell you which part of the sequence you are looking at, and the ordered sets tell you what each side was asking for at that moment.
What is the PIPE interface in PCI Express?
PIPE stands for PHY Interface for PCI Express. It is an interface between the physical layer and the rest of the controller, and it is defined so that a controller can be paired with different PHY implementations without redesigning the whole block. The interface carries the signals that the link layer needs in order to drive the physical layer and to observe what the physical layer is doing.
On the transmit side, PIPE exposes the data path and the control signals that tell the PHY when to send ordered sets, when to send data, and when to enter or leave certain states. On the receive side, it exposes the recovered data, the status of the receiver, and indications about signal detection and alignment. There are also power management signals and clock signals, because the PHY and the controller need to agree on when the interface is active.
The PIPE specification has gone through several versions, and the width of the data path and the set of signals have changed with the supported data rates. A design that targets a given generation of PCI Express will use a PIPE version that matches that generation. When you read a datasheet, the PIPE version is often listed next to the supported link speeds, because the two are tied together.
PIPE is not the same as the link training state machine. LTSSM is a protocol-level sequence that the controller runs, and PIPE is the electrical and logical boundary that lets the controller talk to the PHY while that sequence is running. The two are related, but they live at different levels of the stack.
How do lanes, training, and PIPE fit together?
A useful way to hold the three ideas together is to follow a single link from reset to normal operation. The controller starts the LTSSM sequence. It uses PIPE to ask the PHY to detect a receiver and to begin sending ordered sets. The PHY reports back what it sees, and the controller moves through polling and configuration. The two sides agree on a width, which is the number of lanes that will actually be used. Once the link reaches L0, the same PIPE interface carries the data path for normal traffic.
If you are studying a design or reading a compliance report, it helps to keep the layers separate. The number of lanes is a property of the negotiated link. The training sequence is a set of states and ordered set exchanges. PIPE is the interface that connects the controller to the PHY while all of that happens. Mixing the three up is a common source of confusion when you are trying to read a block diagram or a register map.
What should you check when reading a specification?
Start with the link width and the supported data rates. The specification lists the encodings and the usable bandwidth for each generation, and those numbers depend on the width and the encoding. A x4 link at one generation and a x8 link at another can end up in the same range of usable bandwidth, so the width alone does not tell you the throughput.
Next, look at the LTSSM states that are described. The specification names them and gives the conditions for entering and leaving each one. If a trace shows a link stuck in a particular state, the state name is the first clue about what the link is waiting for.
Finally, check the PIPE version and the signals it defines. The interface is versioned, and the signals that are available depend on the version and the data rate. A design note that lists a PIPE version without the corresponding data rate is incomplete, because the two are chosen together.
None of this requires memorizing the whole specification. It requires knowing which layer a given number belongs to, and reading the definitions in the order the link itself uses them.